View PCA9600_4587674.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PCA9600
Dual bidirectional bus buffer
Rev. 04 -- 11 November 2009 Product data sheet
1. General description
The PCA9600 is designed to isolate I2C-bus capacitance, allowing long buses to be driven in point-to-point or multipoint applications of up to 4000 pF. The PCA9600 is a higher-speed version of the P82B96. It creates a non-latching, bidirectional, logic interface between a normal I2C-bus and a range of other higher capacitance or different voltage bus configurations. It can operate at speeds up to at least 1 MHz, and the high drive side is compatible with the Fast-mode Plus (Fm+) specifications. The PCA9600 features temperature-stabilized logic voltage levels at its SX/SY interface making it suitable for interfacing with buses that have non I2C-bus-compliant logic levels such as SMBus, PMBus, or with microprocessors that use those same TTL logic levels. The separation of the bidirectional I2C-bus signals into unidirectional TX and RX signals enables the SDA and SCL signals to be transmitted via balanced transmission lines (twisted pairs), or with galvanic isolation using opto or magnetic coupling. The TX and RX signals may be connected together to provide a normal bidirectional signal.
2. Features
I Bidirectional data transfer of I2C-bus signals I Isolates capacitance allowing 400 pF on SX/SY side and 4000 pF on TX/TY side I TX/TY outputs have 60 mA sink capability for driving low-impedance or high-capacitive buses I 1 MHz operation on up to 20 meters of wire (see AN10658) I Supply voltage range of 2.5 V to 15 V with I2C-bus logic levels on SX/SY side independent of supply voltage I Splits I2C-bus signal into pairs of forward/reverse TX/RX, TY/RY signals for interface with opto-electrical isolators and similar devices that need unidirectional input and output signal paths I Low power supply current I ESD protection exceeds 4500 V HBM per JESD22-A114, 450 V MM per JESD22-A115, and 1400 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Packages offered: SO8 and TSSOP8 (MSOP8)
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
3. Applications
I Interface between I2C-buses operating at different logic levels (for example, 5 V and 3 V or 15 V) I Interface between I2C-bus and SMBus (350 A) standard or Fm+ standard I Simple conversion of I2C-bus SDA or SCL signals to multi-drop differential bus hardware, for example, via compatible PCA82C250 I Interfaces with opto-couplers to provide opto-isolation between I2C-bus nodes up to 1 MHz I Long distance point-to-point or multipoint architectures
4. Ordering information
Table 1. Ordering information Package Name PCA9600D PCA9600DP SO8 TSSOP8 Description plastic small outline package; 8 leads; body width 3.9 mm plastic thin shrink small outline package; 8 leads; body width 3 mm Version SOT96-1 SOT505-1 Type number
4.1 Ordering options
Table 2. PCA9600D PCA9600DP Ordering options Topside mark PCA9600 9600 Temperature range -40 C to +85 C -40 C to +85 C Type number
5. Block diagram
VCC (2.5 V to 15 V) 8
PCA9600
SX (SDA) 1 3 2 SY (SCL) 7 5 6 4 GND
002aac835
TX (TxD, SDA) RX (RxD, SDA) TY (TxD, SCL) RY (RxD, SCL)
Fig 1.
Block diagram of PCA9600
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
2 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
6. Pinning information
6.1 Pinning
SX RX TX GND
1 2
8 7
VCC SY RY TY
SX RX TX GND
1 2 3 4
002aac837
8 7
VCC SY RY TY
PCA9600D
3 4
002aac836
6 5
PCA9600DP
6 5
Fig 2.
Pin configuration for SO8
Fig 3.
Pin configuration for TSSOP8 (MSOP8)
6.2 Pin description
Table 3. Symbol SX RX TX GND TY RY SY VCC Pin description Pin 1 2 3 4 5 6 7 8 Description I2C-bus (SDA or SCL) receive signal transmit signal negative supply voltage transmit signal receive signal I2C-bus (SDA or SCL) positive supply voltage
7. Functional description
Refer to Figure 1 "Block diagram of PCA9600". The PCA9600 has two identical buffers allowing buffering of SDA and SCL I2C-bus signals. Each buffer is made up of two logic signal paths, a forward path from the I2C-bus interface, pins SX and SY which drive the buffered bus, and a reverse signal path from the buffered bus input, pins RX and RY to drive the I2C-bus interface. These paths:
* sense the voltage state of I2C-bus pins SX (and SY) and transmit this state to pin TX
(and TY respectively), and
* sense the state of pins RX and RY and pull the I2C-bus pin LOW whenever pin RX or
pin RY is LOW. The rest of this discussion will address only the `X' side of the buffer; the `Y' side is identical. The I2C-bus pin SX is specified to allow interfacing with Fast-mode, Fm+ and TTL-based systems.
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
3 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
The logic threshold voltage levels at SX on this I2C-bus are independent of the IC supply voltage VCC. The maximum I2C-bus supply voltage is 15 V. When interfacing with Fast-mode systems, the SX pin is guaranteed to sink the normal 3 mA with a VOL of 0.74 V maximum. That guarantees compliance with the Fast-mode I2C-bus specification for all I2C-bus voltages greater than 3 V, as well as compliance with SMBus or other systems that use TTL switching levels. SX is guaranteed to sink an external 3 mA in addition to its internally sourced pull-up of typically 300 A (maximum 1 mA at -40 C). When selecting the pull-up for the bus at SX, the sink capability of other connected drivers should be taken into account. Most TTL devices are specified to sink at least 4 mA so then the pull-up is limited to 3 mA by the requirement to ensure the 0.8 V TTL LOW. For Fast-mode I2C-bus operation, the other connected I2C-bus parts may have the minimum sink capability of 3 mA. SX sources typically 300 A (maximum 1 mA at -40 C), which forms part of the external driver loading. When selecting the pull-up it is necessary to subtract the SX pin pull-up current, so, worst-case at -40 C, the allowed pull-up can be limited (by external drivers) to 2 mA. When the interface at SX is an Fm+ bus with a voltage greater than 4 V, its higher specified sink capability may be used. PCA9600 has a guaranteed sink capability of 7 mA at VOL = 1 V maximum. That 1 V complies with the bus LOW requirement (0.25Vbus) of any Fm+ bus operating at 4 V or greater. Since the other connected Fm+ devices have a drive capability greater than 20 mA, the pull-up may be selected for 7 mA sink current at VOL = 1 V. For a nominal 5 V bus (5.5 V maximum) the allowed pull-up is (5.5 V - 1 V) / 7 mA = 643 . With 680 pull-up, the Fm+ rise time of 120 ns maximum can be met with total bus loading up to 200 pF. The logic level on RX is determined from the power supply voltage VCC of the chip. Logic LOW is below 40 % of VCC, and logic HIGH is above 55 % of VCC (with a typical switching threshold just slightly below half VCC). TX is an open-collector output without ESD protection diodes to VCC. It may be connected via a pull-up resistor to a supply voltage in excess of VCC, as long as the 15 V rating is not exceeded. It has a larger current sinking capability than a normal I2C-bus device, being able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down capability as well. A logic LOW is transmitted to TX when the voltage at I2C-bus pin SX is below 0.425 V. A logic LOW at RX will cause I2C-bus pin SX to be pulled to a logic LOW level in accordance with I2C-bus requirements (maximum 1.5 V in 5 V applications) but not low enough to be looped back to the TX output and cause the buffer to latch LOW. The LOW level this chip can achieve on the I2C-bus by a LOW at RX is typically 0.64 V when sinking 1 mA. If the supply voltage VCC fails, then neither the I2C-bus nor the TX output will be held LOW. Their open-collector configuration allows them to be pulled up to the rated maximum of 15 V even without VCC present. The input configuration on SX and RX also presents no loading of external signals when VCC is not present. The effective input capacitance of any signal pin, measured by its effect on bus rise times, is less than 10 pF for all bus voltages and supply voltages including VCC = 0 V.
PCA9600_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
4 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
Remark: Two or more SX or SY I/Os must not be interconnected. The PCA9600 design does not support this configuration. Bidirectional I2C-bus signals do not allow any direction control pin so, instead, slightly different logic LOW voltage levels are used at SX/SY to avoid latching of this buffer. A `regular I2C-bus LOW' applied at the RX/RY of a PCA9600 will be propagated to SX/SY as a `buffered LOW' with a slightly higher voltage level. If this special `buffered LOW' is applied to the SX/SY of another PCA9600, that second PCA9600 will not recognize it as a `regular I2C-bus LOW' and will not propagate it to its TX/TY output. The SX/SY side of PCA9600 may not be connected to similar buffers that rely on special logic thresholds for their operation, for example P82B96, PCA9511A, PCA9515A, `B' side of PCA9517, etc. The SX/SY side is only intended for, and compatible with, the normal I2C-bus logic voltage levels of I2C-bus master and slave chips, or even TX/RX signals of a second PCA9600 or P82B96 if required. The TX/RX and TY/RY I/O pins use the standard I2C-bus logic voltage levels of all I2C-bus parts. There are no restrictions on the interconnection of the TX/RX and TY/RY I/O pins to other PCA9600s, for example in a star or multipoint configuration with the TX/RX and TY/RY I/O pins on the common bus and the SX/SY side connected to the line card slave devices. For more details see Application Note AN10658, "Sending I2C-bus signals via long communication cables". The PCA9600 is a direct upgrade of the P82B96 with the significant differences summarized in Table 4.
Table 4. Detail Supply voltage (VCC) range: Maximum operating bus voltage (independent of VCC): Typical operating supply current: Typical LOW-level input voltage on I2C-bus (SX/SY side): LOW-level output voltage on I2C-bus (SX/SY side; 3 mA sink): LOW-level output voltage on Fm+ I2C-bus (SX/SY side; 7 mA sink): Temperature coefficient of VIL / VOL: Logic voltage levels on SX/SY bus (independent of VCC): Typical propagation delays: TX/RX switching specifications compliant): (I2C-bus PCA9600 versus P82B96 PCA9600 2.5 V to 15 V 15 V 5 mA 0.5 V over -40 C to +85 C 0.74 V (max.) over -40 C to +85 C 1 V (max.) 0 mV/C I2C-bus P82B96 2 V to 15 V 15 V 1 mA 0.65 V at 25 C 0.88 V (typ.) at 25 C n/a -2 mV/C
and similar compatible with I2C-bus and similar compatible with buses using TTL levels (SMBus, etc.) buses using TTL levels (SMBus, etc.) < 100 ns < 200 ns yes, all classes including 1 MHz Fm+ yes, all classes including Fm+ yes, 40 % to 55 % (48 % nominal) > 1 MHz > 4500 V SO8, TSSOP8 (MSOP8) yes, 42 % to 58 % (50 % nominal) > 400 kHz > 3500 V DIP8, SO8, TSSOP8 (MSOP8)
RX logic levels with tighter control than I2C-bus limit of 30 % to 70 %: Maximum bus speed: ESD rating HBM per JESD22-A114: Package:
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
5 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
When the device driving the PCA9600 is an I2C-bus compatible device, then the PCA9600 is an improvement on the P82B96 as shown in Table 4. There will always be exceptions however, and if the device driving the bus buffer is not I2C-bus compatible (e.g., you need to use the micro already in the system and bit-bang using two GPIO pins) then here are some considerations that would point to using the P82B96 instead:
* When the pull-up must be the weakest one possible. The spec is 200 A for P82B96,
but it typically works even below that. And if designing for a temperature range -40 C up to +60 C, then the driver when sinking 200 A only needs to drive a guaranteed low of 0.55 V. For the PCA9600, over that same temperature range and when sinking 1.3 mA (at -40 C), the device driving the bus buffer must provide the required low of 0.425 V. larger SX voltage levels then make a better typical match with the driver, even when the supply is as low as 3.3 V. For an I2C-bus compliant driver on 3.3 V the P82B96 is required to guarantee a bus low that is below 0.83 V. P82B96 guarantees that with a 200 A pull-up.
* When the lower operating temperature range is restricted (say 0 C). The P82B96
* When the operating temperature range is restricted at both limits. An I2C driver's
typical output is well below 0.4 V and the P82B96 typically requires 0.6 V input even at +60 C, so there is a reasonable margin. The PCA9600 requires a typical input low of 0.5 V so its typical margin is smaller. At 0 C the driver requires a typical input low of 1.16 V and P82B96 provides 0.75 V, so again the typical margin is already quite big and even though PCA9600 is better, providing 0.7 V, that difference is not big.
8. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages with respect to pin GND. Symbol VCC VI2C-bus VO VI II2C-bus Ptot Tj Tstg Tamb
[1]
Parameter supply voltage I2C-bus voltage
Conditions VCC to GND SX and SY; I2C-bus SDA or SCL TX and TY; buffered output RX and RY; receive input SX and SY; I2C-bus SDA or SCL operating range operating
[1]
Min -0.3 -0.3 -0.3 -0.3 -40 -55 -40
Max +18 +18 +18 +18 250 300 +125 +125 +85
Unit V V V V mA mW C C C
output voltage input voltage I2C-bus current total power dissipation junction temperature storage temperature ambient temperature
[1]
See also Section 10.2 "Negative undershoot below absolute minimum value".
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
6 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
9. Characteristics
Table 6. Characteristics Tamb = -40 C to +85 C unless otherwise specified; voltages are specified with respect to GND with VCC = 2.5 V to 15 V unless otherwise specified. Typical values are measured at VCC = 5 V and Tamb = 25 C. Symbol Parameter Power supply VCC ICC ICC supply voltage supply current additional supply current operating VCC = 5 V; buses HIGH VCC = 15 V; buses HIGH per TX/TY output driven LOW; VCC = 5.5 V 2.5 5.2 5.5 1.4 15 6.75 7.3 3.0 V mA mA mA Conditions Min Typ Max Unit
Bus pull-up (load) voltages and currents Pins SX and SY; I2C-bus VI VO IO IO(sink) IL input voltage output voltage output current output sink current leakage current open-collector; RX and RY HIGH open-collector; RX and RY HIGH static; VSX = VSY = 0.4 V dynamic; VSX = VSY = 1 V; RX and RY LOW VSX = VSY = 15 V; RX and RY HIGH open-collector maximum recommended on buffered bus; VTX = VTY = 0.4 V; SX and SY LOW on I2C-bus = 0.4 V from buffered bus; dynamic; VTX = VTY = 1 V; SX and SY LOW on I2C-bus = 0.4 V on buffered bus; VTX = VTY = VCC = 15 V; SX and SY HIGH from I2C-bus on SX and SY RX and RY HIGH or LOW; SX and SY LOW 1 V RX and RY HIGH; SX and SY HIGH > 1.4 V from buffered bus on RX and RY; SX and SY HIGH or LOW; VRX = VRY = 0.4 V IL leakage current on buffered bus input on RX and RY; VRX = VRY = 15 V
[1] [1]
0.3 7 -
15 -
15 15 2 10
V V mA mA A
Pins TX and TY VO Iload output voltage load current 15 30 V mA
IO
output current
60
130
-
mA
IL
leakage current
-
-
10
A
Input currents II input current -0.3 -1.5 -1 10 -10 mA A A
[1]
[2]
-
-
10
A
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
7 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
Table 6. Characteristics ...continued Tamb = -40 C to +85 C unless otherwise specified; voltages are specified with respect to GND with VCC = 2.5 V to 15 V unless otherwise specified. Typical values are measured at VCC = 5 V and Tamb = 25 C. Symbol Parameter Output logic LOW level Pins SX and SY VOL LOW-level output voltage on Standard-mode or Fast-mode I2C-bus ISX = ISY = 3 mA; Figure 6 ISX = ISY = 0.3 mA; Figure 5 on 5 V Fm+ I2C-bus ISX = ISY = 7 mA V/T voltage variation with temperature ISX = ISY = 0.3 mA to 3 mA Input logic switching threshold voltages Pins SX and SY VIL Vth(IH) V/T VIH Vth(i) VIL V LOW-level input voltage HIGH-level input threshold voltage voltage variation with temperature HIGH-level input voltage input threshold voltage LOW-level input voltage voltage difference fraction of applied VCC fraction of applied VCC fraction of applied VCC SX and SY; SX output LOW at 0.3 mA to SX input HIGH maximum SOT96-1 (SO8); average lead temperature at board interface SX, SY, TX and TY; voltage at which all buses are to be released at 25 C Figure 9
[4]
Conditions
Min
Typ
Max
Unit
-
0.7 0.6 0
0.74 0.65 1 -
V mV V %/K
on normal I2C-bus; Figure 7 on normal I2C-bus; Figure 8
[3]
425 0.55VCC 50
500 500 0 0.48VCC -
580 0.4VCC -
mV mV %/K V V V mV
Pins RX and RY
Logic level threshold difference
Thermal resistance Rth(j-pcb) thermal resistance from junction to printed-circuit board supply voltage 127 K/W
Bus release on VCC failure VCC 1 V
V/T
voltage variation with temperature
-
-4
-
%/K
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
8 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
Table 6. Characteristics ...continued Tamb = -40 C to +85 C unless otherwise specified; voltages are specified with respect to GND with VCC = 2.5 V to 15 V unless otherwise specified. Typical values are measured at VCC = 5 V and Tamb = 25 C. Symbol Parameter Buffer response td time[5] VSX to VTX, VSY to VTY; on falling input between VSX = input switching threshold, and VTX output falling to 50 % VCC VSX to VTX, VSY to VTY; on rising input between VSX = input switching threshold, and VTX output reaching 50 % VCC VRX to VSX, VRY to VSY; on falling input between VRX = input switching threshold, and VSX output falling to 50 % VCC VRX to VSX, VRY to VSY; on rising input between VRX = input switching threshold, and VSX output reaching 50 % VCC Input capacitance Ci input capacitance effective input capacitance of any signal pin measured by incremental bus rise times; guaranteed by design, not production tested 10 pF 50 ns Conditions Min Typ Max Unit
VCC = 5 V; pin TX pull-up resistor = 160 ; pin SX pull-up resistor = 2.2 k; no capacitive load delay time
-
60
-
ns
-
100
-
ns
-
95
-
ns
[1]
The maximum static sink current for a standard I2C-bus is 3 mA and PCA9600 is guaranteed to sink 3 mA at SX/SY when those pins are holding the bus LOW. However, when an external device pulls the SX/SY pins below 1.4 V, the PCA9600 may source a current between 0 mA and 1 mA maximum. During contention an external device is required to pull the bus connected to SX or SY down to the 0.4 V level referenced in the I2C-bus specification. So that device must be able to sink up to 1 mA from SX/SY plus the usual pull-up current. Therefore the external pull-up used at SX/SY should be limited to 2 mA. The typical and maximum currents sourced by SX/SY as a function of junction temperature are shown in Figure 10, and the equivalent circuit at the SX/SY interface is shown in Figure 4. Valid over temperature for VCC 5 V. At higher VCC, this current may increase to maximum -20 A at VCC = 15 V. The input logic threshold is independent of the supply voltage. The minimum value requirement for pull-up current, 0.3 mA, guarantees that the minimum value for VSX output LOW will always exceed the maximum VSX input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC. While the tolerances on absolute levels allow a small probability, the LOW from one SX output is recognized by an SX input of another PCA9600, this has no consequences for normal applications. In any design the SX pins of different ICs should never be linked because the resulting system would be very susceptible to induced noise and would not support all I2C-bus operating modes. The fall time of VTX from 5 V to 2.5 V in the test is approximately 10 ns. The fall time of VSX from 5 V to 2.5 V in the test is approximately 20 ns. The rise time of VTX from 0 V to 2.5 V in the test is approximately 15 ns. The rise time of VSX from 0.7 V to 2.5 V in the test is approximately 25 ns.
[2] [3] [4]
[5]
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
9 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
VCC 1 mA
SX (SY) Vref
002aac838
Fig 4.
Equivalent circuit at SX/SY
800 VOL (mV) 700
(1) (2)
002aac839
800 VOL (mV) 700
002aac840
(1) (2)
600
600
500
500
400 -50
-25
0
25
50
75
100 125 Tj (C)
400 -50
-25
0
25
50
75
100 125 Tj (C)
VOL at SX typical and limits over temperature. (1) Maximum. (2) Typical.
VOL at SX typical and limits over temperature. (1) Maximum. (2) Typical.
Fig 5.
VOL as a function of junction temperature (IOL = 0.3 mA)
001aai060
Fig 6.
VOL as a function of junction temperature (IOL = 3 mA)
001aai061
600 VIL (mV) 500
600 VIH (mV) 500
400
400
300
300
200 -50
-25
0
25
50
75
100 125 Tj (C)
200 -50
-25
0
25
50
75
100 125 Tj (C)
VIL at SX changes over temperature range.
VIH at SX changes over temperature range.
Fig 7.
VIL as a function of junction temperature; maximum values
Fig 8.
VIH as a function of junction temperature; minimum values
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
10 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
1400 VCC(max) (mV) 1200
002aac075
1000 II (A) 800
001aai062
(1) (2)
1000
600
800
400
600
200
400 -50
-25
0
25
50
75
100 125 Tj (C)
0 -50
-25
0
25
50
75
100 125 Tj (C)
(1) Maximum. (2) Typical.
Fig 9.
VCC bus release limit over temperature; maximum values
Fig 10. Current sourced out of SX/SY as a function of junction temperature if these pins are externally pulled to 0.4 V or lower
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
11 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
10. Application information
Refer to PCA9600 data sheet and application notes AN10658 and AN255 for more detailed application information.
VCC (2.5 V to 15 V) 5V I2C-bus SDA TX (SDA) RX (SDA)
R1
'SDA' (new levels)
PCA9600
001aai063
Fig 11. Interfacing a standard 3 mA I2C-bus or one with TTL levels (e.g. SMBus) to higher voltage or higher current sink (e.g. Fast-mode Plus) devices
VCC
VCC1
R2
R4
R5
5V I2C-bus SDA
R1
RX (SDA) TX (SDA)
R3
I2C-bus SDA
PCA9600
001aai064
This simple example may be limited, if using lowest-cost couplers, to speeds as low as 5 kHz. Refer to application notes for schematics suitable for operation to 400 kHz or higher.
Fig 12. Galvanic isolation of I2C-bus nodes via opto-couplers
main enclosure 3.3 V to 5 V 12 V long cables SDA 3.3 V to 5 V 12 V
remote control enclosure 12 V 3.3 V to 5 V
SDA 3.3 V to 5 V
SCL
SCL
PCA9600
PCA9600
002aac846
Fig 13. Long distance I2C-bus communication
PCA9600_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
12 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
+V cable drive VCC1
R2 R2
VCC2 VCC
R2
VCC RX TX TY
R1 R1 R1 R1
RX TX TY
R2
SCL I2C-BUS MASTER SDA
SX
SX
SCL I2C-BUS SLAVE(S)
SY
RY
cable
RY
SY
SDA
PCA9600
C2 C2
PCA9600
propagation delay 5 ns/m
BAT54A BAT54A C2 C2
GND
GND
002aac851
Fig 14. Driving ribbon or flat telephone cables Table 7. Examples of bus capability Refer to Figure 14. VCC1 (V) +V VCC2 cable (V) (V) R1 () R2 C2 (k) (pF) Cable Cable length capacitance (m) Cable delay Set master nominal SCL Effective Max. slave bus clock response speed delay HIGH LOW (kHz) period period (ns) (ns) 600 3850 125 normal specification 400 kHz parts normal specification 400 kHz parts meets Fm+ specification meets Fm+ specification
5
12
5
750
2.2
400
250
n/a (delay based) n/a (delay based) 1 nF 120 pF
1.25 s
5
12
5
750
2.2
220
100
500 ns
600
2450
195
3.3 3.3
5 5
3.3 3.3
330 330
1 1
220 100
25 3
125 ns 15 ns
260 260
770 720
620 690
For more examples of faster alternatives for driving over longer cables such as Cat5 communication cable, see AN10658. Communication at 1 MHz is possible over short cables and > 400 kHz is possible over 50 m of cable.
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
13 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
10.1 Calculating system delays and bus clock frequency
local master bus VCCM
Rm
buffered expansion bus VCCB
Rb Rs
remote slave bus VCCS
MASTER
SCL
SCL
SLAVE
SX
PCA9600
TX/RX
TX/RX
PCA9600
SX
I2C-BUS
Cm Cb Cs
I2C-BUS master bus capacitance buffered bus wiring capacitance slave bus capacitance
002aac847
GND (0 V)
Effective delay of SCL at slave: 120 + 17VCCM + (2.5 + 4 x 109 x Cb) x VCCB + 10VCCS (ns). C = F; V = V.
Fig 15. Falling edge of SCL at master is delayed by the buffers and bus fall times
local master bus VCCM
Rm
buffered expansion bus VCCB
Rb
MASTER
SCL
SX
PCA9600
TX/RX
TX/RX
I2C-BUS
Cm Cb
master bus capacitance GND (0 V)
buffered bus wiring capacitance
002aac848
Effective delay of SCL at master: 115 + (Rm x Cm) + (0.7 x Rb x Cb) (ns). C = F; R = .
Fig 16. Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
14 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
local master bus VCCM
Rm
buffered expansion bus VCCB
Rb Rs
remote slave bus VCCS
MASTER
SDA
SDA
SLAVE
SX
PCA9600
TX/RX
TX/RX
PCA9600
SX
I2C-BUS
Cm Cb Cs
I2C-BUS master bus capacitance buffered bus wiring capacitance slave bus capacitance
001aai158
GND (0 V)
Effective delay of SDA at master: 115 + 0.2(Rs x Cs) + 0.7[(Rb x Cb) + (Rm x Cm)] (ns). C = F; R = .
Fig 17. Rising edge of SDA at slave is delayed by the buffers and bus rise times
Figure 15, Figure 16, and Figure 17 show the PCA9600 used to drive extended bus wiring with relatively large capacitances linking two I2C-bus nodes. It includes simplified expressions for making the relevant timing calculations for 3.3 V or 5 V operation. Because the buffers and the wiring introduce timing delays, it may be necessary to decrease the nominal SCL frequency. In most cases the actual bus frequency will be lower than the nominal Master timing due to bit-wise stretching of the clock periods. The delay factors involved in calculation of the allowed bus speed are: A -- The propagation delay of the master signal through the buffers and wiring to the slave. The important delay is that of the falling edge of SCL because this edge `requests' the data or acknowledge from a slave. See Figure 15. B -- The effective stretching of the nominal LOW period of SCL at the master caused by the buffer and bus rise times. See Figure 16. C -- The propagation delay of the slave's response signal through the buffers and wiring back to the master. The important delay is that of a rising edge in the SDA signal. Rising edges are always slower and are therefore delayed by a longer time than falling edges. (The rising edges are limited by the passive pull-up while falling edges are actively driven); see Figure 17. The timing requirement in any I2C-bus system is that a slave's data response (which is provided in response to a falling edge of SCL) must be received at the master before the end of the corresponding LOW period of SCL as appears on the bus wiring at the master. Since all slaves will, as a minimum, satisfy the worst case timing requirements of their speed class (Fast-mode, Fm+, etc.), they must provide their response, allowing for the set-up time, within the minimum allowed clock LOW period, e.g., 450 ns (max.) for Fm+ parts. In systems that introduce additional delays it may be necessary to extend the minimum clock LOW period to accommodate the `effective' delay of the slave's response. The effective delay of the slave's response equals the total delays in SCL falling edge from
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
15 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
the master reaching the slave (Figure 15) minus the effective delay (stretch) of the SCL rising edge (Figure 16) plus total delays in the slave's response data, carried on SDA, reaching the master (Figure 17). The master microcontroller should be programmed to produce a nominal SCL LOW period as follows:
SCL LOW ( slave response delay to valid data on its SDA + A - B + C + data set-up time ) ns (1)
The actual LOW period will become (the programmed value + the stretching time B). When this actual LOW period is then less than the specified minimum, the specified minimum should be used. Example 1: It is required to connect an Fm+ slave, with Rs x Cs product of 100 ns, to a 5 V Fast-mode system also having 100 ns Rm x Cm using two PCA9600's to buffer a 5 V bus with 4 nF loading and 160 pull-up. Calculate the allowed bus speed: Delay A = 120 + 85 + (2.5 + [4 x 4]) x 5 + 50 = 347.5 ns Delay B = 115 + 100 + 70 = 285 ns Delay C = 115 + 20 + 0.7(100 + 100) = 275 ns The maximum Fm+ slave response delay must be < 450 ns so the programmed LOW period is calculated as: LOW 450 + 347.5 - 285 + 275 + 100 = 887.5 ns The actual LOW period will be 887.5 + 285 = 1173 ns, which is below the Fast-mode minimum, so the programmed LOW period must be increased to (1300 - 285) = 1015 ns, so the actual LOW equals the 1300 ns requirement and this shows that this Fast-mode system may be safely run to its limit of 400 kHz. Example 2: It is required to buffer a Master with Fm+ speed capability, but only 3 mA sink capability, to an Fm+ bus. All the system operates at 3.3 V. The Master Rm x Cm product is 50 ns. Only one PCA9600 is used. The Fm+ bus becomes the buffered bus. The Fm+ bus has 200 pF loading and 150 pull-up, so its Rb x Cb product is 30 ns. The Fm+ slave has a specified data valid time tVD;DAT maximum of 300 ns. Calculate the allowed maximum system bus speed. (Note that the fixed values in the delay equations represent the internal propagation delays of the PCA9600. Only one PCA9600 is used here, so those fixed values used below are taken from the characteristics.) The delays are: Delay A = 40 + 56 + (2.5 + [4 x 0.2]) x 3.3 = 107 ns Delay B = 115 + 50 + 21 = 186 ns Delay C = 70 + 0.7(50 + 30) = 126 ns The programmed LOW period is calculated as: SCL LOW 300 + 117 - 186 + 126 + 50 = 407 ns
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
16 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
The actual LOW period will be 407 + 126 = 533 ns, which exceeds the minimum Fm+ 500 ns requirement. This system requires the bus LOW period, and therefore cycle time, to be increased by 33 ns so the system must run slightly below the 1 MHz limit. The possible maximum speed has a cycle period of 1033 ns or 968 kHz.
12 V 3.3 V to 5 V TX SDA 3.3 V to 5 V TY SCL SY RY SX RX
12 V twisted-pair telephone wires, USB, or flat ribbon cables; up to 15 V logic levels, include VCC and GND
12 V 3.3 V 3.3 V
PCA9600 PCA9600
SX SY
PCA9600
SX SY
PCA9600
SX SY
PCA9600
SY SDA SX SCL
001aai065
SCL/SDA
SCL/SDA
SCL/SDA
no limit to the number of connected bus devices
Fig 18. I2C-bus multipoint application
There is an Excel calculator which makes it easy to determine the maximum I2C-bus clock speed when using the PCA9600. The calculator and instructions can be found at www.nxp.com/clockspeedcalculator.
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
17 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
7 VCC 6 (V) 5 4 3 2 1 0
(2)
002aac932
7 VCC 6 (V) 5 4 3 2
(2) (1)
002aac933
(1)
(1) (2)
1 0
(2)
(1) (2)
-1 0 100 200 300 400 500 600 700 800 900 time (ns)
-1 0 100 200 300 400 500 600 700 800 900 time (ns)
(1) TX output. (2) SX input.
(1) TX/RX output. (2) SX input.
Fig 19. Propagation SX to TX with VRX = VCC = 3.3 V (SX pull-up to 3.3 V; TX pull-up to 5.7 V)
Fig 20. Propagation SX to TX with RX tied to TX; VCC = 3.3 V (SX pull-up to 3.3 V; TX pull-up to 5.7 V)
002aac934
7 VCC 6 (V) 5 4 3
(2) (1)
2
(2)
1 0 -1 0 100 200 300 400 500 600 700 800 900 time (ns)
(1)
(1) RX input. (2) SX output.
Fig 21. Propagation RX to SX (SX pull-up to 3.3 V; VCC = 3.3 V; RX pull-up to 4.6 V)
10.2 Negative undershoot below absolute minimum value
The reason why the IC pin reverse voltage on pins TX and RX in Table 5 "Limiting values" is specified at such a low value, -0.3 V, is not that applying larger voltages is likely to cause damage but that it is expected that, in normal applications, there is no reason why larger DC voltages will be applied. This `absolute maximum' specification is intended to be a DC or continuous ratings and the nominal DC I2C-bus voltage LOW usually does not even reach 0 V. Inside PCA9600 at every pin there is a large protective diode connected to the GND pin and that diode will start to conduct when the pin voltage is more than about -0.55 V with respect to GND at 25 C ambient. Figure 22 shows the measured characteristic for one of those diodes inside PCA9600. The plot was made using a curve tracer that applies 50 Hz mains voltage via a series resistor, so the pulse durations are long duration (several milliseconds) and are reaching peaks of over 2 A when more than -1.5 V is applied. The IC becomes very hot during this
PCA9600_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
18 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
testing but it was not damaged. Whenever there is current flowing in any of these diodes it is possible that there can be faulty operation of any IC. For that reason we put a specification on the negative voltage that is allowed to be applied. It is selected so that, at the highest allowed junction temperature, there will be a big safety factor that guarantees the diode will not conduct and then we do not need to make any 100 % production tests to guarantee the published specification. For the PCA9600, in specific applications, there will always be transient overshoot and ringing on the wiring that can cause these diodes to conduct. Therefore we designed the IC to withstand those transients and as a part of the qualification procedure we made tests, using DC currents to more than twice the normal bus sink currents, to be sure that the IC was not affected by those currents. For example, the TX/TY and RX/RY pins were tested to at least -80 mA which, from Figure 22, would be more than -0.8 V. The correct functioning of the PCA9600 is not affected even by those large currents. The Absolute Maximum (DC) ratings are not intended to apply to transients but to steady state conditions. This explains why you will never see any problems in practice even if, during transients, more than -0.3 V is applied to the bus interface pins of PCA9600. Figure 22 "Diode characteristic curve" also explains how the general Absolute Maximum DC specification was selected. The current at 25 C is near zero at -0.55 V. The PCA9600 is allowed to operate with +125 C junction and that would cause this diode voltage to decrease by 100 x 2 mV = 200 mV. So for zero current we need to specify -0.35 V and we publish -0.3 V just to have some extra margin. Remark: You should not be concerned about the transients generated on the wiring by a PCA9600 in normal applications and that is input to the TX/RX or TY/RY pins of another PCA9600. Because not all ICs that may be driven by PCA9600 are designed to tolerate negative transients, in Section 10.2.1 "Example with questions and answers" we show they can be managed if required.
0 diode current (mA) -10-1
002aaf063
-1
-10
-102
-103
-104 -2.0
-1.5
-1.0
-0.5 0 voltage (V)
Fig 22. Diode characteristic curve
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
19 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
10.2.1 Example with questions and answers
Question: On a falling edge of TX we measure undershoot at -800 mV at the linked TX, RX pins of the PCA9600 that is generating the LOW, but the PCA9600 data sheet specifies minimum -0.3 V. Does this mean that we violate the data sheet absolute value? Answer: For PCA9600 the -0.3 V Absolute Maximum rating is not intended to apply to transients, it is a DC rating. As shown in Figure 23, there is no theoretical reason for any undershoot at the IC that is driving the bus LOW and no significant undershoot should be observed when using reasonable care with the ground connection of the `scope. It is more likely that undershoot observed at a driving PCA9600 is caused by local stray inductance and capacitance in the circuit and by the oscilloscope connections. As shown, undershoot will be generated by PCB traces, wiring, or cables driven by a PCA9600 because the allowed value of the I2C-bus pull-up resistor generally is larger than that required to correctly terminate the wiring. In this example, with no IC connected at the end of the wiring, the undershoot is about 2 V.
6 voltage (V) 4 send
2 receive
0
-2 horizontal scale = 62.5 ns/div time (ns) 5V 5V 300 RX SX TX send 2 meter cable 5V 300 receive GND
002aaf081
PCA9600
Fig 23. Transients generated by the bus wiring
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
20 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
Question: We have 2 meters of cable in a bus that joins the TX/RX sides of two PCA9600 devices. When one TX drives LOW the other PCA9600 TX/RX is driven to -0.8 V for over 50 ns. What is the expected value and the theoretically allowed value of undershoot? Answer: Because the cable joining the two PCA9600s is a `transmission line' that will have a characteristic impedance around 100 and it will be terminated by pull-up resistors that are larger than that characteristic impedance there will always be negative undershoot generated. The duration of the undershoot is a function of the cable length and the input impedance of the connected IC. As shown in Figure 24, the transient undershoot will be limited, by the diodes inside PCA9600, to around -0.8 V and that will not cause problems for PCA9600. Those transients will not be passed inside the IC to the SX/SY side of the IC.
6 voltage (V) 4
2
send 0
receive
-2 horizontal scale = 62.5 ns/div time (ns) 5V 5V 300 RX SX TX send 2 meter cable 5V 300 receive GND
002aaf082
5V
RX TX SX
PCA9600
Fig 24. Wiring transients limited by the diodes in PCA9600
Question: If we input 800 mV undershoot at TX, RX pins, what kind of problem is expected? Answer: When that undershoot is generated by another PCA9600 and is simply the result of the system wiring, then there will be no problems. Question: Will we have any functional problem or reliability problem? Answer: No.
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
21 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
Question: If we add 100 to 200 at signal line, the overshoot becomes slightly smaller. Is this a good idea? Answer: No, it is not necessary to add any resistance. When the logic signal generated by TX or TY of PCA9600 drives long traces or wiring with ICs other than PCA9600 being driven, then adding a Schottky diode (BAT54A) as shown in Figure 25 will clamp the wiring undershoot to a value that will not cause conduction of the IC's internal diodes.
6 voltage (V) 4
2
send 0 receive
-2 horizontal scale = 62.5 ns/div time (ns) 5V 5V 300 RX SX TX send 2 meter cable 5V 300 receive
1/2 BAT54A
5V
RX TX SX GND
002aaf083
PCA9600
Fig 25. Wiring transients limited by a Schottky diode
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
22 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
11. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
D
E
A X
c y HE vMA
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
8o o 0
ISSUE DATE 99-12-27 03-02-18
Fig 26. Package outline SOT96-1 (SO8)
PCA9600_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
23 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
D
E
A
X
c y HE vMA
Z
8
5
A2 pin 1 index
A1
(A3)
A
Lp L
1
e bp
4
detail X wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.45 0.25 c 0.28 0.15 D(1) 3.1 2.9 E(2) 3.1 2.9 e 0.65 HE 5.1 4.7 L 0.94 Lp 0.7 0.4 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 6 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT505-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18
Fig 27. Package outline SOT505-1 (TSSOP8)
PCA9600_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
24 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
12. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
12.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
12.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
12.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
PCA9600_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
25 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
12.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 28) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 8 and 9
Table 8. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 9. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 28.
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
26 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 28. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
13. Abbreviations
Table 10. Acronym CDM ESD HBM I2C-bus I/O IC MM PMBus SMBus TTL Abbreviations Description Charged-Device Model ElectroStatic Discharge Human Body Model Inter-Integrated Circuit bus Input/Output Integrated Circuit Machine Model Power Management Bus System Management Bus Transistor-Transistor Logic
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
27 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
14. Revision history
Table 11. Revision history Release date 20091111 Data sheet status Product data sheet Change notice Supersedes PCA9600_3 Document ID PCA9600_4 Modifications: PCA9600_3 PCA9600_2 PCA9600_1
* *
Table 5 "Limiting values": added Table note [1]. Added Section 10.2 "Negative undershoot below absolute minimum value". Product data sheet Product data sheet Product data sheet PCA9600_2 PCA9600_1 -
20090903 20080813 20080602
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
28 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9600_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2009
29 of 30
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
17. Contents
1 2 3 4 4.1 5 6 6.1 6.2 7 8 9 10 10.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application information. . . . . . . . . . . . . . . . . . 12 Calculating system delays and bus clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 10.2 Negative undershoot below absolute minimum value . . . . . . . . . . . . . . . . . . . . . . . . 18 10.2.1 Example with questions and answers. . . . . . . 20 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 12 Soldering of SMD packages . . . . . . . . . . . . . . 25 12.1 Introduction to soldering . . . . . . . . . . . . . . . . . 25 12.2 Wave and reflow soldering . . . . . . . . . . . . . . . 25 12.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 25 12.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 26 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 28 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 29 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 29 15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 16 Contact information. . . . . . . . . . . . . . . . . . . . . 29 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 November 2009 Document identifier: PCA9600_4

▲Up To Search▲

Price & Availability of PCA9600

	To Download PCA9600 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .